User guide

23-15
SystemVerilog Assertion Constructs
For example:
if (sequence1.triggered)
Level sensitive sequence controls are documented in section 8.11,
starting on page 93, of the SystemVerilog 3.1a Language Reference
Manual.
The following annotated code example shows using a sequence for
these purposes:
module test;
logic l1,l2,clk;
sequence s1;
@ (posedge clk) l1 ##1 l2;
endsequence
Sequence s1 specifies that when there is a rising edge on variable
clk, variable l1 is true, and with the next rising edge on clk, variable
l2 is true.
initial
begin
clk=0;
#4 l1=1;
#10 l2=1;
#3 $finish;
end
always
#5 clk=~clk;
There will be a rising edge on variable clk at time 5 and 15. Simulation
ends at time 17. At the first rising edge, l1 will be true, at the second
rising edge, l2 will be true. The sequence will occur.