User guide

23-14
SystemVerilog Assertion Constructs
Note:
If you are referencing a sequence in another sequence, and you
are using the ended method in the second sequence, the
referenced sequence must specify its clock tick. The first
sequence above does so by beginning with
@(posedge clk).
You cannot use the ended method on a sequence with formal
arguments. Use (or instantiate) such a sequence in another
sequence, and then you can use the method on the other sequence.
For example:
sequence s1(sig3,sig4);
@(posedge clk) sig3 ##1 sig4;
endsequence
sequence s2;
s1(sig3,sig4);
endsequence
sequence s3;
s2.ended ##1 sig1;
endsequence
Level Sensitive Sequence Controls
You can use a SystemVerilog assertion sequence as an event control
expression. You can also use a sequence as the conditional
expression in a wait, if, case, do while, or while statements, if
you use the triggered sequence method.
The triggered sequence method evaluates to true if the sequence
successfully completes during the same time step. You use this
method in an expression that includes the sequence name,
immediately followed by a period (.) and then the keyword
triggered.