User guide

23-13
SystemVerilog Assertion Constructs
Specifying That Sequence Match Within Another
Sequence
You use the within operator to require that one sequence begin
and match when or after another starts but before or when the other
one matches. For example:
sequence s1;
l1 ##3 l4;
endsequence
sequence s2;
l2 ##1 l3;
endsequence
sequence s3;
s2 within s1;
endsequence
Sequence s1 requires three clock ticks, sequence s2 only requires
one clock tick. So it is possible for s2 to begin and end during s1,
signal l2 to toggle to true after l1 does, a clock tick later, l3 toggles to
true, and l4 toggling to true a clock tick later.
Using the End Point of a Sequence
Sequences have an ended method that you can use in another
sequence to specify that the other sequence includes the end of the
first sequence. For example:
sequence s1;
@(posedge clk) sig1 ##1 sig2;
endsequence
sequence s2;
s1.ended ##1 sig3;
endsequence