User guide

23-12
SystemVerilog Assertion Constructs
Sequence s3 succeeds when either sequences s1 and s2 succeed
but only when sequences s1 and s2 start at the same time.
Only Looking For the First Match Of a Sequence
The first_match operator specifies that a sequential expression
matches only once. After its first success, VCS no longer looks for
subsequent matches.
sequence s1;
first_match(l1 ##[1:2] l2);
endsequence
In s1, if l1 is true at the first clock tick, the expression could match at
the next clock tick, or the one after that, but the use of the
first_match operator means that VCS does not monitor for the
second possible match if the first possible match occurs.
Conditions for Sequences
You can use the throughout operator to specify a condition that
must be met throughout the sequence in order for the sequence to
succeed. For example:
sequence s1;
(sig3 || sig4) throughout sig1 ##1 sig2;
endsequence
For this sequence to succeed, not only must sig1 be true and then in
the next clock tick, sig2 be true, but also for both clock ticks the
expression
(sig3 || sig4) must evaluate to true.