User guide

23-10
SystemVerilog Assertion Constructs
$fell(expression)
If the expression is just a signal, this returns 1 if the least significant
bit of the signal changed to 0 between clock ticks. If the expression
is more than one signal and an operator, for example sig1 +
sig2, this returns 1 if the value of the least significant bit in the
evaluation of the expression changes from 1, X, or Z to 0.
$stable(expression)
Returns 1 if the value of the expression does not change between
clock ticks. A change in a four state signal from X to Z returns false.
The following is an example of using these system functions:
sequence s1;
$rose(sig1) ##1 $stable(sig2 && sig3);
endsequence
Anding Sequences
You can use the and operator to specify that two sequences must
occur (succeed), but not necessarily at the same time. The following
is an example:
sequence s1;
sig1 ##1 sig2;
endsequence
sequence s2;
sig3 ##2 sig4;
endsequence
sequence s3;
s1 and s2;
endsequence
Sequence s3 succeeds when both sequences s1 and s2 succeed.
The time of the success of s3 is whenever the last of s1 or s2 succeed.