User guide

23-9
SystemVerilog Assertion Constructs
The above expression would pass the following sequence, assuming
that 3 is within the min:max range.
a c c c c b c c b c b d d d c
Specifying a Clock
You can specify a clock in a sequence. For example:
sequence s1;
@(posedge clk) sig1 ##1 sig2;
endsequecle
This sequence specifies that the clock tick is on the rising edge of
signal clk.
Value Change Functions
You can also include the following system functions in a sequential
expression. They tell you about value changes between clock ticks:
$sampled(expression)
Returns the sampled value of the expression with respect to the
last occurrence of the clocking event.
$rose(expression)
If the expression is just a signal, this returns 1 if the least significant
bit of the signal changed to 1 between clock ticks. If the expression
is more than one signal and an operator, for example sig1 +
sig2, this returns 1 if the value of the least significant bit in the
evaluation of the expression changes from 0, X, or Z to 1.