User guide

23-7

SystemVerilog Assertion Constructs

sig1 ##1 sig2 ##1 sig2 ##1 sig2;

endsequence

Can be shortened to the following:

sequence s1;

sig1 ##1 sig2 [*3];

endsequence

Note:

The value you specify with the [* operator must be a positive

integer.

You can use repetition in a range of clock ticks. For example:

sequence s1;

(sig1 ##2 sig2) [*1:3];

endsequence

This sequence specifies that the sequence is run at the length of itself,

or the length of itself doubled, or tripled. This sequence is the

equivalent of all of the following:

sequence s1;

(sig1 ##2 sig2);

endsequence

sequence s1;

(sig1 ##2 sig2 ##1 sig1 ##2 sig2);

endsequence

sequence s1;

(sig1 ##2 sig2 ##1 sig1 ##2 sig2 ##1 sig1 ##2 sig2);

endsequence