User guide

23-6
SystemVerilog Assertion Constructs
The operands in the sequences need to be boolean expressions, they
do not have to be just signal names. For example:
sequence s1;
sig1 == 1 ##1 sig3 || sig4;
endsequence
Unconditionally Extending a Sequence
You can unconditionally extend a sequence by using the literal true
value 1 or a text macro defined as 1. For example:
sequence s2;
sig1 ##1 sig2 ##2 !sig3 ##3 1;
endsequence
Here sig1 must be true, one clock tick later sig2 must be true, then
two clock ticks later sig3 must be false, but the sequence doesn’t end
until three clock ticks later. Extending a sequence can be handy when
you are using a sequence in another sequence.
Using Repetition
There are three operators for specifying the repetition of a sequence:
• The consecutive repetition operator [*
• The goto repetition operator [->
• The non-consecutive repetition operator [=
The consecutive repetition operator [* is for specifying consecutive
repetitions of a sequence. For example, the following sequence:
sequence s1;