User guide

23-5
SystemVerilog Assertion Constructs
•At $root (in SystemVerilog $root means outside of any other
definition, a sequence defined in $root is globally accessible).
Note:
The SystemVerilog LRM says that you can declare a sequence
in a module definition but never in an always or initial block.
Using Formal Arguments In A Sequence
You can specify formal arguments in a sequence and then make
substitutions when you use it in another sequence. For example:
sequence s1(sig3,sig4);
sig3 ##1 sig4;
endsequence
sequence s2;
s1(sig1,sig2) ##1 sig5;
endsequence
Specifying a Range of Clock Ticks
You can specify a range of clock ticks in the delay. For example:
sequence s1;
sig1 ##[1:3] sig2;
endsequence
This sequence specifies that sig1 must be true and then sig2 must
be true at either the first, second, or third subsequent clock tick.
You can specify that the range end at the end of the simulation with
the $ token, for example:
sequence s1;
sig1 ##[1:$] sig2;
endsequence