User guide

23-4
SystemVerilog Assertion Constructs
Sequence s1 specifies that signal sig1 is true and then one clock tick
later signal s2 is true. In this case the clock signal and the edge that
specifies the clock tick, are in a property definition that instantiates
this sequence. The ## operator specifies a delay of a number of clock
ticks (the value you specify must be a non-negative integer).
You can specify any number of signals in the sequential expression
and the logical negation operator. For example:
sequence s2;
sig1 ##1 sig2 ##2 !sig3;
endsequence
Sequence s2 specifies that signal sig1 must be true, and one clock
tick later signal s2 must be true, and then two clock ticks after that
signal s3 must be false.
You can use a sequence in another sequence as a building block in
another sequence, for example:
sequence s1;
sig1 ##1 sig2;
endsequence
sequence s3;
s1 ##2 !sig3;
endsequence
Here sequence s1 is used in sequence s3.
You can declare a sequence in the following places in your code:
• In a module definition
• In an Interface definition