User guide

23-3
SystemVerilog Assertion Constructs
In this example the immediate assertion is labeled a1, and its
expression (lg1 && lg2 && lg3) is the condition. If the condition
is true, VCS executes the begin-end block labeled pass. This is the
pass action block (it is not required to name this action block). If the
condition is not true, VCS executes the begin-end block labeled fail
(it is also not required to name this action block), it follows the keyword
else.
If, for example, this immediate assertion passes, the condition is true,
and VCS displays the following:
test.named.a1 passed
Concurrent Assertions Overview
Concurrent assertions consists of one or more properties. A property
consists of a clock signal and one or more sequences. In a property
you can either specify a sequence of values on signals and the
simulation time that occurs between these values, specified as clock
ticks, or instantiate a sequence that you declare. You can declare a
sequence and then use it as a building block in a property.
Sequences
A sequence enables you to build and manipulate sequential behavior.
The following is an example of a sequence:
sequence s1;
sig1 ##1 sig2;
endsequence