User guide

23-2
SystemVerilog Assertion Constructs
Concurrent assertions specify how the design behaves during a span
of simulation time.
Immediate Assertions
An immediate assertion resembles a conditional statement in that it
has a boolean expression that is a condition. When VCS executes
the immediate assertion it tests this condition and if it is true, VCS
executes some statements in what is called a pass action block. If
the condition is not true VCS executes statements in what is called
a fail action block.
The following is an example of an immediate assertion:
module test;
.
.
.
initial
begin:named
.
.
.
a1:assert (lg1 && lg2 && lg3)
begin: pass
$display("%m passed");
.
.
.
end
else
begin: fail
$display("%m failed");
.
.
.
end
end