User guide

23-1
SystemVerilog Assertion Constructs
23
SystemVerilog Assertion Constructs 1
SystemVerilog assertions (SVA), just like OpenVera assertions
(OVA), are a shorthand way to specify how you expect a design to
behave and have VCS display messages when the design does not
behave as specified. You can use both to accomplish the same thing.
SystemVerilog assertions are in the SystemVerilog 3.1a standard
promulgated by Accellera, the electronics industry wide organization
for the advancement of hardware description languages. OpenVera
assertions are part of the Synopsys proprietary OpenVera standard.
VCS has implemented both types of SystemVerilog assertions:
• Immediate assertions
• Concurrent assertions
Immediate assertions are a test of an expression when VCS executes
the immediate assertion. An immediate assertion is a statement in
procedural code.