User guide

22-69
SystemVerilog Design Constructs
This module uses the method called parity, using the syntax:
interface_instance_name.method_name
Enabling SystemVerilog
You tell VCS to compile and simulate SystemVerilog code with the
-sverilog compile-time option. No runtime option is necessary.
IMPORTANT:
Radiant Technology (+rad) does not work with
SystemVerilog design construct code, for example
structures and unions, new types of always blocks,
interfaces, or things defined in $root.
The only SystemVerilog constructs that work with Radiant
Technology are SystemVerilog assertions that refer to
signals with Verilog-2001 data types, not the new data types
in SystemVerilog.
Disabling unique And priority Warning Messages
By default VCS displays warning messages in certain situations when
you enter unique if, unique case, priority if and priority
case statements. For example:
RT Warning: More than one conditions match in 'unique if'
statement.
" filename.v", line line_number, at time sim_time
RT Warning: No condition matches in 'unique if' statement.
" filename.v", line line_number, at time sim_time