User guide

22-67
SystemVerilog Design Constructs
Now let’s modify the module definition for module sendmod:
In the module header, in the connection list in the header where using
the interface is declared, the modport is also declared, using the
following syntax:
interface_name.modport_name
Module receivemod is also modified:
module receivemod(intf.receivemode intfb1,
input logic [7:0] in,
output logic [7:0] out);
always @(intfb1.send) out = intfb1.send;
always @(intfb1.send) intfb1.receive = in;
endmodule
Modports also control the visibility of signals declared in an interface.
If a signal in an interface is not specified in a modport, then modules
that use the modport cannot access the signal.
module sendmod (intf.sendmode intfa1,
input logic [7:0] in,
output logic [7:0] out);
always @(intfa1.receive) out = intfa1.receive;
always @(intfa1.receive) intfa1.send = in;
endmodule
modport follows the
interface name