User guide

22-65
SystemVerilog Design Constructs
and interface definitions can be in module definitions or nested in
other interface definitions.
• To use an interface to connect a module instance to another, you
must instantiate the interface in the module that instantiates the
two module instances.
• You also must declare the interface in the port connection list of
the module headers of the two modules you are connecting with
the interface. Note that the interface instance names in the port
connection lists do not have to match the interface instance name
in the module that instantiates these module, not do the instance
names have to match in the port connection lists of the modules
connected by the instance. In this example we have the following
instance names for the same interface: intf1, intfa1, and intfb1.
• To read from or write to a signal in an interface, you reference it
by interface_instance_name.signal_name.
This basic example, meant only to introduce interfaces, doesn’t do
much to show you the utility of an interface. In fact, in this example
the signals in the interface, send and receive, are functionally the
same as inout ports in the module definitions and two nets with the
wire data type connecting these inout ports.
What if your intent is for the instance of module sendmod to always
send data to module receivemod through one signal, in this case
signal send, and receive data from module receivemod from the other
signal, signal receive? This basic interface isn’t doing the job for you.
You can use an interface construct called a modport to add
directionality to signals in an interface.