User guide

22-64
SystemVerilog Design Constructs
Example 22-5 Basic Interface
As illustrated in this example:
• In the VCS implementation, interface definitions must be in the
$root declaration space, outside of any module definition. In the
Accellera SystemVerilog 3.1a specification, this is not the case,
interface intf;
wire [7:0] send,receive;
endinterface
module test;
logic [7:0] data_in1, data_in2, data_out1, data_out2;
intf intf1();
sendmod sm1 (intf1, data_in1, data_out1);
receivemod rm1 (intf1, data_in2, data_out2);
endmodule
module sendmod (intf intfa1,
input logic [7:0] in,
output logic [7:0] out);
assign out = intfa1.receive;
assign intfa1.send = in;
endmodule
module receivemod(intf intfb1,
input logic [7:0] in,
output logic [7:0] out);
assign out = intfb1.send;
assign intfb1.receive = in;
endmodule
Interface defined in $root
Interface instantiated in module definition
Connect module instance to
interface instance
Reading from a signal in
an interface
Writing to a signal in
an interface
Interface
declared in
module
header