User guide

22-63
SystemVerilog Design Constructs
At its simplest level, an interface encapsulated communication like a
struct encapsulates data:
Think of a wire as a built-in interface.
An interface is like a module that straddles other modules.
Interfaces help you to maintain your code. For example, to add a
signal between blocks in your design, you only need to edit the
interface instead of editing the module headers of both modules and
the module instantiation statements for these modules.Interfaces are
not just wires. Interfaces can contain the following:
• Variables and parameters that can be declared in one location
and used in various modules.
• Tasks or functions that can be used by all instances that connect
to these interfaces.
• Procedures for checking and other verification operations.
Example 22-5 introduces a basic interface and the code that uses it.
typedef struct{
int int1;
logic [7:0] log1;
} s_type;
interface intf;
int int1;
wire [7:0] w1;
endinterface
module module
interface