User guide

22-61
SystemVerilog Design Constructs
endmodule
In module refportmod the port named refin1 is declared with the ref
keyword. All operations done in module refportmod to ref port refin1
also happen to the value of the highconn signal, int1, in module test.
The $monitor system task in module test displays the following:
int1 = x at 0
int1 = 100 at 10
int1 = 50 at 11
int1 = 66 at 20
int1 = 33 at 21
int1 = 24 at 30
int1 = 12 at 31
The value of integer int1 is halved because it is connected to a ref
port in a module that halves this port.
A ref port is the only way to share a variable value across the
hierarchy.
Both the ref port and the highconn signal must have the same
variable data type.
A ref port differs from an inout port in that an inout port must
have a net data type, whereas a ref port must have a variable data
type.