User guide

22-60
SystemVerilog Design Constructs
Ref Ports on Modules
Like arguments to tasks that you declare with the ref keyword, you
can declare module ports with the ref keyword instead of the input,
output, or inout keywords.
A ref port is a reference to the signal that connects to it in a module
instantiation statement in a higher level module instance. This
connected higher-level signal is called a highconn signal. for a ref
port there isn’t separate simulation values for the highconn signal and
the instance’s port, with values propagating to the port from the signal
or to the signal from the port. VCS only has one copy of the simulation
data for both the highconn signal and the ref port. All operations that
the module does to its ref port it also does directly to the highconn
signal.
The following is an example of the use of a ref port:
`timescale 1 ns / 1 ns
module refportmod (ref integer refin1);
always @ refin1
#1 refin1 = refin1/2;
endmodule
module test;
integer int1;
initial
begin
$monitor("int1 = %0d at %0t",int1,$time);
#10 int1 = 100;
#10 int1 = 66;
#10 int1 = 24;
end
refportmod refportmod1 (int1);