User guide

22-59
SystemVerilog Design Constructs
as asterisk to connect the signals to the ports, similar to an implicit
event control expression list for an always block. For example:
module top;
logic [7:0] log1;
byte byt1 [1:0];
dev dev1(.*);
endmodule
module dev(input byte byt1 [1:0], input logic [7:0] log1);
.
.
.
endmodule
New Port Connection Rules for Variables
SystemVerilog allows you to declare an input port to be a variable.
This is another way to use a structural driver, see "Writing To
Variables" on page 22-19. If you declare an input port to be a
variable, you cannot have multiple drivers, so you cannot do any of
the following:
• Assign values to the variable with a procedural assignment
statement or a user-defined task enabling statement.
• Assign values to it with a continuous assignment statement or
have values propagate to it from a module instance, gate,
switch-level primitive, or UDP.
Like Verilog-2001 and Verilog-1995, SystemVerilog allows you to
declare an output port to be a variable and prohibits the same for
inout ports.