User guide

22-58
SystemVerilog Design Constructs
Instantiation Using Implicit .name Connections
In SystemVerilog if the name and size of a port matches the name
and size of the signal that connects to that port, you can make
connections in any order without matching the order of the ports or
using a name based connection list where you have to enter each
port and the signal that connects to it. For example:
module top;
logic [7:0] log1;
byte byt1 [1:0];
dev dev1(.log1,.byt1);
endmodule
module dev(input byte byt1 [1:0], input logic [7:0] log1);
.
.
.
endmodule
Module top instantiates module dev. In the module instantiation
statement in module top, the connection list has signal log1 first,
followed by signal byt1. In the module header for module dev, the
port connection list has port byt1 first followed by port log1.
In Verilog-2001 or Verilog-1995 you would need a name-based
connection list in the module instantiation statement:
dev dev1(.log1(log1),.byt1(byt1));
Instantiation Using Implicit .* Connections
In SystemVerilog, if the name and size of a port matches the name
and size of the signal that connects to that port, you use a period and