User guide

22-57
SystemVerilog Design Constructs
module mod1(input int in1, byte in2, inout wire io1, io2,
output mystruct out);
.
.
.
endmodule
In the module header for module mod1:
1. The first port is named in1. It is specified as an input port with
the int data type.
- If we omitted both the direction and data type, SystemVerilog
expects the port to be declared following the header.
- If only the direction is omitted, it defaults to inout.
- If only the data type is omitted, it defaults to the wire net data
type (which you can change with the ‘default_nettype
compiler directive to another net data type).
2. The second port is named in2. No direction is specified so it
inherits the direction from the previous port, so in2 is an input
port with the byte data type.
3. The third port is named io1. It’s specified as an inout port with
the wire data type.
4. The fourth port is named io2. Not being the first port in the list, it
inherits the direction and data type from port io1.
5. The last port is named out. It is an output port that is the structure
mystruct.
You still can only use net data types for inout ports.
The Accellera SystemVerilog 3.1a specification says that named
events can also be ports, but this is not implemented in VCS.