User guide

22-56
SystemVerilog Design Constructs
wire [7:0] send, receive;
endinterface
module top1(w1);
output w1;
endmodule
module top2(w1);
input w1;
endmodule
All constructs that are declared or defined in $root are, for the most
part, accessible to the entire design. Any module, regardless of its
place in the hierarchy, can use the parameter, use the type, read or
write to these variables, use the named event, call the task and
function, or instantiate the interface. The gate and switch primitive
cannot be instantiated in the rest of the design (they are already
instantiated in $root) but the rest of the design can write to their
inputs and read their outputs. The UDP can be instantiated in the rest
of the design. The module definitions, not instantiated elsewhere, are
top-level modules. Note that they connect to $root level wire w1.
New Data Types for Ports
In SystemVerilog a module input or output port can be any net
data type or any variable data type including an array, a structure, or
a union. For example:
typedef struct {
bit bit1;
union packed{
int int1;
logic log1;
} myunion;
} mystruct;