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22-55

SystemVerilog Design Constructs

parameter msb=7;

typedef int myint;

wire w1,w2,w3,w4;

logic clk;

and and1 (w2,w3,w4);

tran tr1 (w1,w4);

primitive prim1 (out,in);

input in;

output out;

table

// in : out

0 : x;

1 : 0;

x : 1;

endtable

endprimitive

event recieved_data;

task task1 (input [3:2][1:0]in1, in2, output bit

[3:2][1:0]out);

logic tlog1,tlog2;

tlog1=in1[3][1];

.

.

.

#10 out[3][1]=tlog1;

.

.

.

tlog2=in2;

endtask

function void left (output myint k);

k = 34;

$display ("entering left");

endfunction

interface try_i;