User guide

22-54
SystemVerilog Design Constructs
The extern declaration declares the user-defined function.
The address of the int variable i is passed to the user-defined task
because the argument of the task has the inout direction.
The printf statements display the following:
before export, i=4
after export, i=2
Hierarchy
SystemVerilog contains enhancements for representing the design
hierarchy:
• The $root top-level global declaration space
• New data types for ports
• Instantiation using implicit .name connections
• Instantiation using implicit .* connections
• New port connection rules for variables
The $root Top-Level Global Declaration Space
In SystemVerilog there is the $root top-level declaration space
which not only contains all uninstantiated modules, but also interface
definitions (in the current implementation interface definitions cannot
be inside module definitions or other interfaces), user-defined tasks
and functions, parameter, nets and variables, and type definitions.
Some examples of $root declarations are as follows: