User guide

22-50

SystemVerilog Design Constructs

module mod1;

import pack1::*;

struct1 mod1struct1;

struct1 mod1struct2;

struct1 mod1struct3;

struct1 mod1struct4;

initial

begin

mod1struct1.real1=5;

mod1struct1.real2=11;

mod1struct2.real1=3;

mod1struct2.real2=7;

#10 mod1struct3 = halvfunc1 (mod1struct1);

#10 mod1struct4 = halvfunc1 (mod1struct2);

#10 $display("mod1struct3.real1=%0f",mod1struct3.real1);

#10 $display("mod1struct3.real2=%0f",mod1struct3.real2);

#10 $display("mod1struct4.real1=%0f",mod1struct4.real1);

#10 $display("mod1struct4.real2=%0f",mod1struct4.real2);

end

endmodule

The $display system tasks display the following:

mod1struct3.real1=2.500000

mod1struct3.real2=5.500000

mod1struct4.real1=1.500000

mod1struct4.real2=3.500000

Exporting Time Consuming User-Defined Tasks with the

SystemVerilog DPI

You can export a user-defined task that contains delays into the C or

C++ language using the DPI. Such a user-defined task consumes

simulation time and does not start and finish its execution during the

same simulation time step.