User guide

22-49
SystemVerilog Design Constructs
initial begin
#1 top_bool_value1 = top_bool_value2;
#5 top_bool_value2 = FALSE;
end
initial
$monitor("%0t top_bool_value1=%0d top_bool_value2=%0d",
$time, top_bool_value1, top_bool_value2);
endmodule
The $monitor system task displays the following
0 top_bool_value1=0 top_bool_value2=1
1 top_bool_value1=1 top_bool_value2=1
6 top_bool_value1=1 top_bool_value2=0
The following package contains a structure and a user-defined
function:
package pack1;
typedef struct {real real1, real2;} struct1;
function struct1 halvfunc1 (struct1 in1);
halvfunc1.real1 = in1.real1 / 2;
halvfunc1.real2 = in1.real2 / 2;
endfunction
endpackage : pack1
The following module definition begins with the following:
1. A wildcard character in the import statement to specify
referencing both the structure and the user-defined function in the
module
2. Four declarations of instances of the structure