User guide

22-48
SystemVerilog Design Constructs
#6 int1=7;
endmodule
Modules top1 and top2 share int1 in package pack1. They both
declare the use of the variable with import statements that reference
both the package and the variable. The $monitor system task
displays the following:
int1=0 at 0
int1=7 at 6
int1=11 at 10
Both modules top1 and top2 assign values to int1.
Note:
A data type declaration in a package is different from a data type
declaration in $root. you must reference a data type in a package
with an import statement before you can assign values to it.
The following package declares a user-defined data type.
package pack1;
typedef enum { FALSE, TRUE } bool_values;
endpackage
The following module definition references the user-defined data type
and the values of the user defined data type using import
statements:
module top;
import pack1::bool_values;
import pack1::FALSE;
import pack1::TRUE;
bool_values top_bool_value1;
bool_values top_bool_value2 = TRUE;