User guide

22-47
SystemVerilog Design Constructs
You define a SystemVerilog package between the package and
endpackage keywords. You must specify an identifier for the
package. This package declares int variable int1.
A module, macromodule, interface, or program references something
declared in a package with an import statement with the :: scope
resolution operator.
You can also use an import statement, with the :: scope resolution
operator, in a package, to reference the contents of another package,
but you can’t use it to reference something in a module, macromodule,
interface, or program. The following is an example of a package
referencing something in another package:
package pack2;
import pack1::int1;
endpackage
What follows are two module definitions that share what is declared
in package pack1:
module top1;
import pack1::int1;
initial
begin
$monitor ("int1=%0d at %0t", int1, $time);
#10 int1=11;
#10 $finish;
end
endmodule
module top2;
import pack1::int1;
initial