User guide

22-46
SystemVerilog Design Constructs
In the first location, the argument overrides the default and the second
default value is applied as if the function call were written as:
func1(2, 300);
SystemVerilog Packages
A package is a scope that contains declarations of things that you
want to share with more than one module, macromodule, interface
or program.
Note:
- A SystemVerilog package is a concept borrowed from VHDL.
- Classes in packages are an LCA feature requiring a special
license.
- SystemVerilog assertion sequence and property declaration in
packages, and referencing them in a module or program
definition, is not supported yet.
The things that you can declare in a package are data types, including
complex data types like structures, and user-defined tasks and
functions.
The following are examples of a package definitions and how to
reference things declared in a package:
package pack1;
int int1;
endpackage