User guide

22-43
SystemVerilog Design Constructs
• in2 is a scalar port that takes both defaults, input direction and
the logic data type.
•out is an output port so the direction must be specified. It is of
the int data type so that too is specified. In SystemVerilog a
function can have an output or an inout port.
int funcint;
Local scalar variable funcint is declared, with the int data type. Ports
have a default data type, local variables do not.
funcint = in1[3] >> 1;
.
.
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out = funcint;
.
.
.
if (in2==0)
return 0;
outgo = funcint;
Notice that, just like SystemVerilog tasks, these assignment
statements are not inside a begin end or fork join block. By
default, statements in a function are executed sequentially, just like
they were in a begin end block. If you want, you can enclose these
statements in a begin end or fork join block.
In these procedural statements:
1. The local variable funcint is assigned a shifted value of an element
in the multi-dimensional array of input port in1.
2. The new value of funcint is assigned to the output port named out.
3. SystemVerilog functions can have a return statement that
overrides an assignment to the function name. Here if input port
in2 equals zero, the function returns zero.