User guide

22-42
SystemVerilog Design Constructs
function reg [1:0] outgo(reg [3:2][1:0] in1,in2, output int
out);
int funcint;
funcint = in1[3] >> 1;
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.
.
if (in2==0)
return 0;
out = funcint;
.
.
.
outgo = funcint;
endfunction
initial
begin
.
.
.
#1 reg2=outgo(reg1,log1,int2);
.
.
.
end
Lets take a look at a number of lines in the function:
function reg [1:0] outgo(reg [3:2][1:0] in1,in2, output int
out);
The function header specifies that the function name is outgo. It
declares that it returns a two-bit value of the reg data type (a
SystemVerilog function can also return a multi-dimensional array, or
a structure or union). The default data type of the return value is
logic. The header declares three ports:
• in1 is an input port of the reg data type. It is a multi-dimensional
packed array. In SystemVerilog, function ports, like task ports,
can be a multi-dimensional array. Also, like task ports, function
ports default to the input direction, so port in1 is an input port.