User guide

22-41
SystemVerilog Design Constructs
instead of
input [3:2][1:0] in1
• in2 takes both defaults. The default direction is an input port and
the default data type is logic.
• out deviates from both defaults and so it must be specified as an
output port with the bit data type. It is also a multi-dimensional
packed array.
logic tlog1,tlog2;
Local scalar variables tlog1 and tlog2 are declared, with the logic
data type. Ports have a default data type, local variables do not.
tlog1=in1[3][1];
.
.
.
#10 out[3][1]=tlog1;
.
.
.
tlog2=in2;
Notice that these assignment statements are not inside a begin end
or fork join block. By default statements in a task are executed
sequentially, just like they were in a begin end block. If you want,
you can enclose these statements in a begin end or fork join
block.
Functions
The following is an example of a valid SystemVerilog function and
the code that calls the function. Note the differences from what would
be a Verilog-2001 function.