User guide

22-40
SystemVerilog Design Constructs
• Returning values from a task or function before executing all the
statements in a task or function
Tasks
The following is an example of a valid SystemVerilog task. Note the
differences from what would be a Verilog-2001 task.
task task1 (input [3:2][1:0]in1, in2, output bit
[3:2][1:0]out);
logic tlog1,tlog2;
tlog1=in1[3][1];
.
.
.
#10 out[3][1]=tlog1;
.
.
.
tlog2=in2;
endtask
Lets take a look at a number of lines in the task:
task task1 (input [3:2][1:0]in1, in2, output bit
[3:2][1:0]out);
The task header declares three ports:
• in1 is declared as an input port. The keyword input is
necessary only because it is a multi-dimensional packed array. In
SystemVerilog a port can be a multi-dimensional array, packed
or unpacked. In SystemVerilog task ports also have data types.
The default data type is logic, so in1 has the logic data type.
If in1 were an unpacked multi-dimensional array, you would not
need the keyword input to make it an input port:
in1 [3:2][1:0]