User guide

2-18
Modeling Your Design
Inferring Faster Simulating Sequential Devices
VCS is optimized to simulate sequential devices. If VCS can infer that
an always block behaves like a sequential device, VCS can simulate
the always block much faster.
The IEEE Std 1364-2001 defines always constructs on page 149.
Verilog users commonly use the term always block when referring
to an always construct.
VCS can infer whether an always block is a combinatorial or
sequential device. This section describes the basis on which VCS
makes this inference.
Avoid unaccelerated statements
VCS does not infer an always block to be a sequential device if it
contains any of the following statements:
Statement Description in IEEE Std 1364-2001
force and release
procedural statements
Page 126-127
repeat statements
Page 134-135, see the other looping statements
on these pages and consider them as an
alternative.
wait statements, also called
level-sensitive event controls
Page 141
disable statements
Page 162-164
fork-join block statements, also
called parallel blocks
Page 146-147