User guide

22-39
SystemVerilog Design Constructs
q <= d;
An always_ff block can only have one event control.
The final Block
The final block is a counterpart to the initial block. The final block
executes during the last simulation time step in the simulation. A final
block cannot contain delay specifications, non-blocking assignments,
event controls, wait statements or contain user-defined task enabling
statements for tasks that contain these constructs. The following is
an example of a final block:
final
begin
mytask (l1,l2);
$display(" simulation ends at %0t",$time);
end
Final blocks are an LCA feature requiring a special license.
Tasks and Functions
SystemVerilog changes tasks and functions in the following ways:
• Easier ways to declare task and function ports
• Function inout and output ports
• Void functions
• Tasks no longer requiring begin end or fork join blocks