User guide

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SystemVerilog Design Constructs
The always_latch Block
The always_latch block models latched behavior, combinational
logic with storage. The following is an example of an always_latch
block:
always_latch
if (clk) sigq <= sigd;
The always_latch block is similar to the always_comb block in
the following ways:
• It has an inferred sensitivity list. It executes when there is a
transition in the signals in the right-hand side of assignment
statements.
• There can be no other assignment statements in the design that
assign values to the variables in the left-hand side of its
assignment statements.
• It always executes at time zero.
The difference between the always_latch and always_comb
block is for synthesis. It’s a way to make clear that you intend a latch
for the code in the always_latch block.
The always_ff Block
The always_ff block models synthesizable sequential behavior.
The following is an example of an always_ff block:
always_ff @(posedge clk or negedge reset)
if (!reset)
q <= 0;
else