User guide

22-37
SystemVerilog Design Constructs
var1 = sig1 + sig2;
else
var1 = sig1 - sig2;
var2 = sig1 + sig2;
end
This always block executes at time zero only because there were
transitions on the signals in its implicit sensitivity list at time zero, in
this example on signals sig1 and sig2. If there were to such time zero
transitions, this always block would not execute at time zero. The
always_comb block always executes at time zero so the
always_comb block more accurately models proper wired logic
behavior.
Another difference between such an always block and a similar
always_comb block is that an always_comb block executes after
all the always and initial blocks execute at time zero. The
always block with and implicit event control expression list, if it
executes at time zero, executes in no predictable order with the other
always or initial blocks that execute at time zero.
If you have more than one always_comb block, there is no way to
predict the order in which they execute at time zero other than that
they execute after the always and initial blocks that execute at
time zero.
You can consider an always_comb block. For example:
always_comb
bit1 = bit2 || bit3;
assign wire1 = bit1;
To be analogous to a continuous assignment statement:
assign wire1 = bit2 || bit3;