User guide

22-36
SystemVerilog Design Constructs
if (!mode)
var1 = sig1 + sig2;
else
var1 = sig1 - sig2;
var2 = sig1 + sig2;
end
SystemVerilog uses the term sensitivity list and in an always_comb
block, the signals in the right-hand side of the assignment statements
are inferred to be in the sensitivity list, meaning that any transition in
these signals causes the execution of the always_comb block. In
this example any transition in signals sig1 and sig2 cause the always
block to execute.
To make sure that there is consistency between the expressions on
the right-hand side of the assignments and the variables on the
left-hand side, an always_comb block also executes at time zero,
after the initial and always blocks that start at time zero begin
executing.
There is a rule that there cannot be any other procedural assignment
statements in the rest of the design that assign values to variables
on the left-hand side of the assignment statements in an
always_comb block. In this example there can be no other
assignment statements in the design assigning values to var1 and
var2.
An alway_comb block is similar to the always block with and implicit
event control expression list. For example:
bit sig1 = 1;
bit sig2 = 1;
always @*
begin
if (!mode)