User guide

22-35
SystemVerilog Design Constructs
Here VCS repeatedly does these two things: increments signal i1 and
then check to see if signal r1 is at 0. If when it checks r1 is no longer
at 0, it stops incrementing i1. With a while statement, VCS would
check on r1 before incrementing i1.
SystemVerilog Processes
SystemVerilog identifies the Verilog always block and its three
variations, as static processes (There are dynamic processes that
are not yet implemented). These three variations are as follows:
• always_comb
• always_latch
• always_ff
SystemVerilog also sees continuous assignment statements as static
processes and you can use them to continuously assign to not just
nets but also variables.
SystemVerilog also has a final block that executes during the last
simulation time step.
The always_comb Block
An alway_comb block models combinational logic. This block is to
circumvent the problem of an always block with a missing else
statement resulting in an unintended latch. The following is an
example of an always_comb block:
always_comb
begin