User guide

22-34
SystemVerilog Design Constructs
RT Warning: More than one conditions match in 'unique case'
statement.
" filename.v", line line_number, at time sim_time
If none of the case item expressions have the value of the case
expression, it is also a warning condition and VCS displays the
following warning message:
RT Warning: No condition matches in 'unique case' statement.
" filename.v", line line_number, at time sim_time
The keyword priority preceding a case, casex, or casez
statement specifies that one case item expression must have the
value of the case expression. So in the following code:
priority case (l4)
0: $display("l4 !1");
1: $display("l4=%0d",l4);
endcase
If l4’s value is neither 0 or 1, it is a warning condition and VCS
displays the following warning message:
RT Warning: No condition matches in 'priority case'
statement.
" filename.v", line line_number, at time sim_time
The do while Statement
SystemVerilog has the do while statement. It’s an alternative to the
Verilog while statement, where an action is performed and then a
condition is evaluated. Here is an example:
do #1 i1++; while (r1 == 0);