User guide

22-33
SystemVerilog Design Constructs
VCS evaluates these conditional expressions in sequence to see if
they are true. VCS executes the first statement controlled by the first
conditional expression that is true. In this example, therefore, VCS
would display:
l4!=0
The priority keyword allows more than one conditional expression
to be true. In this example the conditional expression
(l4==3)could
also be true but this would not be a warning condition.
If neither conditional expression were true, it would be a warning
condition and VCS displays the following warning message:
RT Warning: No condition matches in 'priority if' statement.
" filename.v", line line_number, at time sim_time
The keyword unique preceding a case, casex, or casez statement
specifies that one, and only one, case item expression can have the
value of the case expression.
So in the following code:
unique case (l2)
0: $display("l2=%0d",l2);
1: $display("l2=%0d",l2);
!0: $display("l2 also !0");
endcase
There is the case expression l2 and three case item expressions: 0,
1, and !0.
VCS evaluates these case item expressions in parallel and, if more
than one has the value of the case expression, it is a warning condition
and VCS displays the following warning message: