User guide

22-32
SystemVerilog Design Constructs
Statements
The keyword unique preceding an if or nested else if statement
specifies that one, and only one, conditional expression must be true.
So in the following code:
unique if (l2!=0) $display("l2!=0");
else if (l2==3) $display("l2=3");
There are two conditional expressions: (l2!=0) and (l2==3).
VCS evaluates these conditional expressions in parallel and, if both
are true, it is a warning condition and VCS displays the following
warning message:
RT Warning: More than one conditions match in 'unique if'
statement.
" filename.v", line line_number, at time sim_time
If neither conditional expression is true, it is also a warning condition
and VCS displays the following warning message:
RT Warning: No condition matches in 'unique if' statement.
" filename.v", line line_number, at time sim_time
The keyword priority preceding an if or nested else if
statement specifies that one conditional expression must be true. So
in the following code:
priority if (l4!=0) $display("l4!=0");
else if (l4==3) $display("l4=3");
There are two conditional expressions: (l4!=0) and (l4==3).