User guide

22-31
SystemVerilog Design Constructs
=+ -= *= /= %= &= |= ^= <<= >>= <<<= >>>=
The following table shows a few uses of these assignment operators
and their equivalent in Verilog-2001.
SystemVerilog includes the ++ increment and -- decrement
operators. The following table shows how they work.
You can place the ++ and -- operators to the left or the right of the
variable operand. Doing so makes a difference when these operators
and their operand are in a larger expression, but enabling you to do
so is not yet implemented in VCS, so you can only use them as simple
assignment statements.
New Procedural Statements
In SystemVerilog if and case statements, including casex and
casez, can be qualified by the unique or priority keywords and
there is a do while statement.
The unique and priority Keywords in if and case
operator example Verilog-2001 equivalent
b += 2; b = b + 2;
b -= 2; b = b - 2;
b *= 2; b = b * 2;
operator example Verilog-2001 equivalent
++b; or b++;
b = b + 1;
--b;
or b--;
b = b - 1;