User guide

22-29
SystemVerilog Design Constructs
• VPI force and release should behave exactly in the same manner
as procedural statement force and release.
• If the vpi_put_value call contains a time delay information, VCS
ignores it.
• If the vpi_put_value call contains a value with vpiReleaseFlag,
VCS ignores the value argument of vpi_put_value.
• You cannot apply vpi_put_value to an entire struct. You can only
apply it to individual members.
In the following example, SystemVerilog code makes a PLI call
$forceX. In the PLI code, the SystemVerilog variables in that module
are iterated and once the handle of the required variable is obtained,
vpi_put_value is used with vpiForceFlag to force a value on to the
variable. In the example, value 7 is forced on the variable through an
argument (value_s) of vpi_put_value function call.
module dut(input int I, output int O);
int y;
always @(I) begin
#10 y = I + 50; // 2
.
.
.
#20 $forceX(); // 3
.
.
.
#20 $releaseX(); // 4
end
endmodule
// PLI code
.
.
.
void forceX()
{
vpiHandle var;
int flag = vpiForceFlag;