User guide

22-28
SystemVerilog Design Constructs
typedef struct{
int int1;
bit [31:0] packedbit;
integer intg1;
} unpackedstruct;
typedef struct packed{
logic [2:0] log1;
bit [2:0] bit1;
}packedstruct;
module test;
unpackedstruct ups1;
unpackedstruct ups2;
packedstruct ps1;
packedstruct ps2;
assign ups1.int1=30;
initial
begin
#0 ups1.packedbit[0]=0;
#20 force ups1.int1=1;
#20 force ups2=ups1;
#20 release ups2.int1;
#20 release ups2;
#20 force ps1.log1=1;
#20 force ps1.bit1=0;
#20 force ps2=ps1;
#20 release ps1;
end
endmodule
Using the VPI
You can force and release on SystemVerilog variables using the VPI.
The following conditions apply: