User guide

22-27
SystemVerilog Design Constructs
Like with force statements, you can enter a release statement for
an entire array, a slice of elements in the array, or a single element.
You can use a variable to specify the element of an unpacked array.
For example:
int int1;
logic l1 [2:0];
initial
begin
int1=2;
force l1[int1]=3;
end
If however, you have and unpacked array of packed bits, the packed
bits must be specified with a value or a parameter, not a variable. For
example:
int int1=1;
parameter p1=4;
logic log1 [2:0];
logic [5:3]log2[2:0];
initial
begin
force log1[int1]=1;
force log2[int1][p1]=1;
end
The const constant construct will not work for specifying packed bits.
Structures
You can force and release both entire packed and unpacked
structures, or individual members of the structure. For example: