User guide

22-26
SystemVerilog Design Constructs
Unpacked Arrays
You can make force statements to an element of an unpacked array
or a slice of elements. For example:
int int1;
logic l1 [2:0];
bit bit1 [2:0];
reg reg1 [2:0];
byte byte1 [2:0];
int int2 [2:0];
shortint si1[2:0];
longint li1[2:0];
integer intg1[2:0];
initial
begin
int1=2;
force l1[int1]=3;
force bit1[int1]=3;
force reg1[int1]=3;
force byte1[int1]=3;
force int2[int1]=3;
force si1[int1]=3;
force li1[int1]=3;
force intg1[int1]=3;
end
You can force an entire unpacked array, a slice of elements, or a
single element. For example:
int int1 [2:0];
int int2 [2:0];
initial
begin
force int1={1,1,1};
force int2[2:1]=int1[2:1];
force int2[0]=0;
end