User guide

22-25

SystemVerilog Design Constructs

The following are examples of these data type declarations and valid

force statements to the most significant bits in them:

shortint si1;

int int1;

longint li1;

byte byte1;

bit [31:0] bit1;

logic [31:0] log1;

reg [31:0] reg1;

integer intg1;

initial

begin

force si1[15]=1;

force int1[31]=1;

force li1[63]=1;

force byte1[7]=1;

force bit1[31]=1;

force log1[31]=1;

force reg1[31]=1;

force intg1[31]=1;

end

Notice that a bit-width was not specified for the shortint, int,

longint, byte, or integer data types in their declarations, but

these force statements to these bit-selects are valid. This is because

these data types have a known number of bits, with little-endian

numbering.

Force statements to bit or part-selects of the real, time, or

realtime data types are not possible.